The present invention relates in general to computer system memories. More particularly, the invention is directed to systems and methods for using spare bits in the context of a global memory shared by a multiplicity of processors.
Systems composed of multiple but coordinated processors were first developed and used in the context of mainframes. More recently, interest in multiple processor systems has escalated as a consequence of the low cost and high performance of microprocessors, with the objective of replicating mainframe performance through the parallel use of multiple microprocessors.
A variety of architectures have been defined for multi-processor systems. Most designs rely upon highly integrated architectures by virtue of the need for cache coherence. In such systems, cache coherence is maintained through complex logic circuit interconnection of the cache memories associated with the individual microprocessors to ensure data consistency as reflected in the various caches and main memory.
A somewhat different approach to architecting a multi-processor system relies upon a relatively loose hardware level coupling of the individual processors, with the singular exception of circuit logic controlling access to the shared global memory, and the use of software to manage cache coherence. An architecture which relies upon software managed cache coherence allows the designer to utilize existing processor hardware to the maximum extent, including the utilization of memory error correction resources such as bank related spare bit steering and data error correction code (ECC) memory configurations. This relative independence of the processors also lends itself to multi-processor systems with extenuated levels of availability, in that one or more processors may be disconnected without disrupting the operation of the remaining processors. Coordination in the access to, and coherency with, a shared global memory is of course somewhat more difficult when the processors are not closely coupled.
One problem that arises with a shared global memory, loosely coupled, multi-processor architecture relates to the management of error detection and correction resources. In such context, the designation and coordinated use of spare bits as well as error correction code bits must be consistent from processor to processor, so that the data in global memory is both consistent and reliable.